IEEE 1801

Design and Verification of Low-Power, Energy-Aware Electronic Systems
DESIGN AND VERIFICATION OF LOW-POWER, ENERGY-AWARE ELECTRONIC SYSTEMS
Errata to Design and Verification of Low-Power Integrated Circuits
Design and Verification of Low-Power Integrated Circuits-Amendment 1
Design and Verification of Low-Power Integrated Circuits
Design and Verification of Low Power Integrated Circuits

: IEEE

: 1110000250563

:

Format
$449.00

Publication Date: 12/05/2015 - Complete Document *

Description :

This standard defines the syntax and semantics of a format used to express power intent in energy-aware electronic system design. Power intent includes the concepts and information required for specification and validation, implementation and verification, and modeling and analysis of power-managed electronic systems. This standard also defines the relationship between the power intent captured in this format and design intent captured via other formats (e.g., standard hardware description languages and cell libraries).

Purpose

The standard enables portability of power intent across a variety of commercial products throughout an electronic system design, analysis, verification, and implementation flow.

Document Type : Complete Document

Edition : IEEE Computer Society

Language : English

Page Count : 515

Publication Date : 12/05/2015

Revision : 15

Status : Current

Title : Design and Verification of Low-Power, Energy-Aware Electronic Systems

Publication Date: 09/23/2014 - Complete Document

Document Type : Complete Document

Page Count : 402

Publication Date : 09/23/2014

Revision : 13

Status : Historical

Title : DESIGN AND VERIFICATION OF LOW-POWER, ENERGY-AWARE ELECTRONIC SYSTEMS

Publication Date: 09/23/2014 - Amendment *

Document Type : Amendment

Edition : IEEE Computer Society

Language : English

Page Count : 2

Publication Date : 09/23/2014

Revision : 13

Status : Historical

Title : Errata to Design and Verification of Low-Power Integrated Circuits

Publication Date: 08/21/2014 - Amendment *

Description :

The set of changes required to address technical and editorial errors that have been identified in IEEE Std 1801-2013 are specified in this amendment. In addition this amendment also specifies a few changes and enhancements to remove some ambiguities and inconsistencies related to the semantics of power states, power supplies, precedence rules, and location of power management cells.

Document Type : Amendment

Edition : IEEE Computer Society

Language : English

Page Count : 52

Publication Date : 08/21/2014

Revision : 13

Status : Historical

Title : Design and Verification of Low-Power Integrated Circuits-Amendment 1

Publication Date: 03/06/2013 - Base Document *

Description :

This standard establishes a format used to define the low-power design intent for electronic systems and electronic intellectual property (IP). The format provides the ability to specify the supply network, switches, isolation, retention, and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low-power design specification and the logic design specification captured via other formats [e.g., standard hardware description languages (HDLs)].

Purpose The standard provides portability of low-power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification, and implementation flow.

Document Type : Base Document

Edition : IEEE Computer Society

Language : English

Page Count : 351

Publication Date : 03/06/2013

Revision : 13

Status : Historical

Title : Design and Verification of Low-Power Integrated Circuits

Publication Date: 03/19/2009 - Complete Document *

Description :

Foreword

The purpose of this standard is to provide the electronic design automation (EDA), semiconductor, and system design communities with a well-defined and official IEEE unified hardware design, specification, and verification standard language. The language is designed to coexist and enhance the hardware description languages (HDLs) presently used by designers while providing the capabilities lacking in those languages.

SystemVerilog is a unified hardware design, specification, and verification language that is based on the Accellera SystemVerilog 3.1a extensions to the Verilog HDL [B1]a, published in 2004. Accellera is a consortium of EDA, semiconductor, and system companies. IEEE Std 1800 enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows.

SystemVerilog enables the use of a unified language for abstract and detailed specification of the design, specification of assertions, coverage, and testbench verification that is based on manual or automatic methodologies. SystemVerilog offers application programming interfaces (APIs) for coverage and assertions, a vendor-independent API to access proprietary waveform file formats, and a direct programming interface (DPI) to access proprietary functionality. SystemVerilog offers methods that allow designers to continue to use present design languages when necessary to leverage existing designs and intellectual property. This standardization project will provide the VLSI design engineers with a well-defined IEEE standard that meets their requirements in design and validation and enables a step function increase in their productivity. This standardization project will also provide the EDA industry with a standard to which they can adhere and which they can support in order to deliver their solutions in this area.

Scope

This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI).

Throughout this standard, the following terms apply:

— Verilog refers to IEEE Std 1364 for the Verilog HDL.

— Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.

— Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.

— SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this standard.

Scope

This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI).

Throughout this standard, the following terms apply:

— Verilog refers to IEEE Std 1364 for the Verilog HDL.

— Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.

— Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.

— SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this standard.

Document Type : Complete Document

Edition : IEEE Computer Society

Language : English

Page Count : 234

Publication Date : 03/19/2009

Revision : 09

Status : Historical

Title : Design and Verification of Low Power Integrated Circuits